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Statistical Variability: software rules CMOS

Thursday 9th February 2012
Simulation of statistical variability in 22 nm CMOS technology transistors uses software GSS 3D statistical ‘atomistic’ simulator GARAND

Gold Standard Simulations CEO Professor Asen Asenov is to deliver the keynote talk on variability in emerging CMOS technologies at the March VAMM workshop, part of Design, Automation and Test in Europe (DATE) conference inDresden, Germany . The Workshop is on Variability modelling and mitigation techniques in current and future technologies (VAMM) vital for semiconductor development.

“We can deliver a significant competitive advantage to our customers by screening and selecting the best technology options for them, reducing  development cost and time and shortening the time-to-market for new technologies” says (right) Professor Asenov. 

DATE is organised by three large European projects focused on variability aware technology, transistors and circuit co-design in contemporary and future CMOS technology generations. The projects are MODERN, TRAMS and Synaptic, all lying behind future computer hard and software developments.

Statistical variability and reliability introduced by Random Discrete Dopants (RDD), Line Edge Roughness (LER), Metal Gate Granularity (MGG), and random Interface Trapped Charge (ITC) in bulk MOSFETs is one of the major roadblocks to device scaling and integration.



It is expected that at 22nm it will have a detrimental impact on both SRAM area and supply voltage scaling making the design of properly-scaled low-leakage SRAM virtually impossible. Transistor architectures that tolerate low channel doping can substantially reduce statistical variability, putting SRAM area and supply voltage scaling back on track. Unsurprisingly, in May 2011 Intel announced the introduction of FinFETs (Tri-Gate transistors) for their 22nm technology generation
.
For the first time, there is an essential branching in the semiconductor industry with both bulk MOSFET, FinFET and FDSOI-based CMOS coexisting and competing at the 22nm technology generation. There is also a distinct possibility that modifications to the conventional bulk MOSFET, which utilise low-doped epitaxial channels, will also start to compete.

COMPARE & CONTRAST 
Accordingly it is essential to be able to compare performance and variability of the main competing technologies - conventional and epitaxial bulk MOSFETs, FinFETs and FD-SOI MOSFETs - for at least three technology generations.

Such comparison is of great importance for two reasons:
(i) It will help technology providers (IDMs and foundries) make the correct technology choices that provide a solution to the critical problems associated with variability, for not one, but two or more technology generations.

(ii) With more than one technology option available from different providers, fabless companies must be able to make the right technology choices that meet the specific requirements of their products.

GSS, Ltd is the only company that provides a fully integrated service and tool chain that allows device/circuit co-design and comparison of contemporary and future CMOS technology options including:  

  • predictive simulation of statistical variability with  ‘atomistic’ TCAD device simulator GARAND,  
  • extremely accurate statistical compact model extraction and generation with Mystic  
  •  seamless statistical circuit simulation/analysis with flexible circuit simulation engine RandomSpice.

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