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SOI FinFETs for 11nm CMOS

Monday 5th December 2011
Room for the GARAND-enabled simulation of statistical variability in a 22 nm FinFET subject to gate and fin line edge roughness, random discrete dopants, metal gate granularity and interface trapped charge.

University of Glasgow and Gold Standard Simulations (GSS), presented a joint paper at the IEDM this week to reveal that Silicon On Insulator (SOI) FinFETs are poised to meet low statistical variability requirements of 11nm CMOS technology. Simulations were carried out using the GSS statistical ‘atomistic’ simulator GARAND, which delivers unprecedented accuracy in predictive physical simulation of statistical variability in modern transistors.

Statistical CMOS variability introduced by discreteness of charge and atomicity of matter now rules theCMOS world. Statistical variability in ‘bulk’ MOSFETs, dominated by random discrete dopants, has dramatically increased device leakage and has slowed the scaling of supply voltage in the last four CMOS technology generations, fueling the power crisis. As a result statistical variability has become a major driver for the introduction of new, variability resistant, MOSFET architectures.

The hard-hitting variability crisis first impacted SRAM yield and leakage, which forced Intel to introduce FinFETs at 22nm although there is no FinFET intel paper at IEDM. Intelligence suggests Intel are facing significant difficulties and may have to delay 22nm FinFETs introduction and tolerate lower channel doping when compared to conventional ‘bulk’ MOSFETs and exhibit reduced statistical variability and associated CMOS leakage. Intel’s move sparked the Transistor Wars between FinFETs and fully depleted (FD) SOI transistors, both claiming to provide a life-line to stalling CMOS scaling.

Although the ‘bulk’ FinFETs to be introduced by Intel are built on a conventional silicon substrate, FinFETs built on an SOI substrate could have significant advantages in terms of simpler processing, better process control and reduced statistical variability. The GU/GSS paper shows that the statistical variability in ‘well tempered’ 10 nm SOI FinFETs can be kept below the statistical variability in 45 nm bulk CMOS technology.

According to the Professor Asen Asenov, CEO of GSS, Ltd. “In the war between future transistor architectures, predictive physical simulation of statistical variability delivers significant competitive advantages. For technology providers, the decision of which of the competing architectures to adopt will be determined by the capabilities of the technology to deliver scale benefits for at least two generations.

"GSS has a simulation tool chain that can facilitate these important decisions by providing accurate physical simulations of competing transistor architectures, and also accurate statistical compact model extraction and statistical circuit simulation tools to help understand their impact on design.”  

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