SWAN is one of four nanoelectronics centers funded through the Nanoelectronics Research Initiative (NRI), a program of the Semiconductor Research Corporation (SRC) comprised of global semiconductor companies with a vested interest in going beyond Moore’s law. 

NRI members, Texas Instruments, Intel, Global Foundries, IBM and Micron,  partner with the National Institute of Standards and Technology and the National Science Foundation to fund research projects through the country.

Over the the last four years, Dr Bhagawan Sahu has developed much underlying knowledge of nanoscale graphene behavior through numerical simulations on Ranger supercomputer at Texas Advanced Computing Center (TACC).

Dr Sahu has investigated single-layer, bilayer, and multilayer forms of graphene and experimented, virtually, with different widths, lengths, layer orientations, layer stackings and external voltages for graphene ribbons and flakes, to see how variables influence such electronic properties as the electron band gap, magnetism and related factors.

SWAN have now selected a graphene-based collective charge system. The device structure, the bilayer pseudospintronic field-effect transistor (BiSFET), is based on two layers of graphene separated by a super-thin insulator or air or a vacuum.

In the device, pseudospin refers to the presence of charge either on the top layer or the bottom layer, much like electron “spin” in quantum mechanics, which can take two possible values. The physics of the device is based on collective charge motion, which forms a superfluid state at room temperature under certain conditions.

“The simulations are playing a major role in elucidating the interplay of the structure and the electronic properties of graphene,” Dr Sahu said. “We’re building component by component, so we have an integrated view of what each part does and how it affects the whole device.”

The flurry of research into graphene sees it as a potential material for memory systems, for clean energy lithium-ion battery and solar photovoltaic cells. Common to all these applications. a need for smaller, faster, more energy efficient devices and novel materials.

“Energy is one of the pressing problems for the society, and a lot of energy is consumed in present digital devices,” said Dr. Sahu. “If we can design a device that uses a billion times less power than a silicon transistor, as BisFET seems to promise, we can build on that kind of technology for the next few generations after 2020."

“Understanding the device components atomistically through simulations has become inevitable in these nanoscale devices,” Dr. Sahu said. “Our efforts at SWAN provide the community with the simulation results, which are obtained by virtual experiments before any real experiments are performed.”

Prof. Allan MacDonald at The University of Texas at Austin proposed the theory behind BisFET. Prof. Sanjay K. Banerjee (director of the SWAN center), Prof. Leonard F. Register, and Dr. Emanuel Tutuc, also from UT-Austin, explored the device design and metrics in depth.

The simulations necessary to understand the formation of the superfluid phase in graphene bilayers are now carried out by Prof. Register’s group and Dr Sahu’s simulations have been crucial to understanding the internal and external variables that can affect the device performance.

“Atomistic simulations are necessary to understand the nanoscale effects arising from metal-graphene and metal-dielectric contacts,” Dr Sahu said.

The collective motion of the charge carriers in BisFET devices have an advantage over current silicon systems: more charges can be collected using less voltage, increasing performance and decreasing device overall power consumption.

Next  Discovery Phase
In 2013, the SRC hopes that one or two nanotransistor designs will emerge as promising enough to justify expanded work on proof-of-concept demonstrations. This will require extensive research, initially in the university centers and eventually in industry labs.

Even if all goes well, it will be challenging to introduce these devices into products by 2020, since it often takes 10 years or more from initial discovery to commercial implementation for new technology.

If the devices use very different materials or structures, this will be no small endeavor. To convert fabrication facilities from silicon to graphene, for example, is expected to cost billions of US dollars. That is, if it is even possible to produce graphene in large enough quantities to realise carbon age electronics.

Efforts by another SWAN member, Prof. Rodney S. Ruoff,  University of Texas at Austin, working with Texas Instruments' SWAN assignee, Dr. Luigi Colomboto, to grow large area graphene films on metal substrates by chemical vapor deposition, which is critical for the success of the center’s BisFET device.

Graphene defect flowers in strength
NRI member, NIST researchers  have recently also found that defects in graphene are caused by the movement of carbon molecules during the manufacture of graphene from silicon carbide under high temperature and high vacuum conditions. 

Of all the possible rearrangements of atoms, the easiest requiring minimum energy is the formation offive or member rings from six-member rings. The NIST team has discovered that this re-arrangement creates a new defect in the honey comb lattice of graphene.

Eric Cockayne, NIST researcher, explains that when graphene is subjected to extreme heat,  parts of the lattice come loose and start rotating.  When the temperature is  lowered, the loose sections  re-attach in a haphazard manner with the lattice. The daisy-like defect patterns formed by this increases the strength of graphene.

Cockayne notes that further experiments could lead to finding the  relationship between the appearance of the defect and the growth variations.