In February this year, Glasgow University led by Professor Asen Asenov (right) of the Department of Electronic and Electrical Engineering formed a key role on the €3.4m Tera-scale Reliable Adaptive Memory Systems (TRAMS) consortium. This includes Intel Corp, Iberia, IMEC, Brussels, and the coordinators Universitat Politecnica de Catalunya, to focus on delivering reliable, energy efficient and cost effective computing, and also consider the ‘Beyond CMOS’ technologies of nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, expected to be in the five nanometres frame. That project expects to last three years.

Now the Device Modelling Group DMG  at Glasgow University, which is a world leader in the simulation and forecasting of statistical variability, isinvited as a key partner in the corresponding ENIAC MOdelling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN) proposal. This  is part of the funding package designed to support the DMG participation in ENIAC MODERN and includes funding from ENIAC, EPSRC and Scottish Enterprise.

It affirms the UK's leadership position in this field, but more important, will make available the associated knowledge, expertise and simulation tools to the vibrant UK CMOS device and design communities and will give a competitive advantage to the UK design industry.

It will also train experts at the 'interface' between technology, devices and design, much needed in the UK chipless and fabless design companies ( ARM, CSR, Wofson Microelectronics) and the numerous UK SMEs with chip design activities.

Increased variability is a problem which presents a huge barrier to the continued scaling of microchips and the development of ever-more powerful computers and electronic systems. MODERN is to develop new design tools and methodology for transistors and circuits at the nanoscale which will enable the manufacturing of reliable, low cost, low electromagnetic interference, high-yield complex silicon chips and corresponding products using unreliable and variable devices

Professor Asenov, device modelling expert in electronics and electrical engineering and leading world authority in statistical complementary metal-oxide semiconductor variability, is again leading Glasgow’s involvement in the project,  worth £1.5m to the University and consists of some 28 European partners.

Specifically, the main goals of the MODERN project are:
• 1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures.
• 2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance.
◦ Reliability, noise, EMC/EMI.
◦ Timing, power and yield.
• 3. Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.
• 4. Validation of the modelling and design methods and tools on a variety of silicon demonstrators.

In the MODERN consortium the University of Glasgow is to provide key expertise in the physical simulation of statistical variability and reliability, statistical compact model extraction and statistical circuit simulation.
Simulations will be conducted using leading edge variability simulation tools developed in the Glasgow Device Modelling Group over the last 10 years and will involve the recently established spin-out company, Gold Standard Simulation which will be providing services to the MODERN project.

Prof Asenov said: “We invested heavily in variability research and in the development of variability simulation tools at a time when the industry was not fully aware of the gravity of the forthcoming variability problem. Now we are in the position to make significant contribution in tackling the variability challenge”.

David Jack, Project manager at Scottish Enterprise, said: "This project will reinforce the University of Glasgow's position at the forefront of technology which will be built into many new electronic products. The formation of spin-out company, Gold Standard Simulations Ltd, demonstrates that Scotland's growing businesses have a strong opportunity to lead the electronics industry of the future."

EPSRC Chief Executive, Dave Delpy (left)  said “Working with Scottish Enterprise we are delighted to have enabled the UK to participate in this ambitious and potentially high impact project. This collaboration is an excellent example of the union of world leading research and a delivery partner that can provide powerful economic impact and accelerates our path to prosperity.”