‘Tera-scale Reliable Adaptive Memory Systems’ (TRAMS) consortium includes: Intel Corporation Iberia, Interuniversitair Micro-Elektronica Centrium vzw, (IMEC), University of Glasgow, and coordinators Universitat Politecnica de Catalunya, financed through the EU’s Framework Programme (FP7) science research fund.

Within the next decade, microchips are expected to shrink in size while offering vaster, terascale computing capabilities that will transform not only the throughput of large data centers and computing facilities but also power, performance and functionality of personal computers, communication devices, computer games and other consumer electronics products.

But individual nanoscale transistors in the future terascale chips will be much more susceptible to manufacturing faults, have unprecedented variability and be more unreliable. The FP7 TRAMS project will be the bridge to delivering reliable, energy efficient and cost effective computing in the era of nanoscale and teraflop.

Professor Asen Asenov (right) nicknamed the 'Decanano' professor for his long term focus on the variability in 10nm or smaller device sizes, is a world-leading authority on variability of Complementary Metal-Oxide Semiconductors (CMOS) transistors and microchips.

“Tera-scale computing will transform the power, performance and functionality of personal computers, phones and other electronic devices as well as large computing facilities such as data centres," he says. “However, if we are to continue to shrink the size of transistors in order to develop such powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors.

“We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively, heralding the era of tera-scale computing.”

Central to the project is simulation software developed by Prof Asenov and his team in an earlier £5.3m Engineering and Physical Sciences Research Council eScience pilot project called NanoCMOS, whose simulations used grid computing to simulate how hundreds of thousands of transistors, each with their own individual characteristics, will function within a circuit.

Now Prof Asenov and University of Glasgow are setting up Gold Standard Simulations (GSS),  a company to exploit this technology, which will be critical to the work of the TRAMS project, with all device design and simulation work being conducted at Glasgow.

In investigating design possibilities for future microchips, the team will focus on future generation of CMOS microchip technologies - transistors less than 16 nanometres in size - which will be designed and simulated exclusively by Glasgow.

The TRAMS consortium will also consider what are known as ‘Beyond CMOS’ technologies; nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, expected to be in the five nanometres frame.

The project is expected to last three years.