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EU DIAMOND approach to parallel TRAMS

Saturday 20th February 2010
Radiant cut diamond: Courtesy:http://www.stellarjewelry.com/diamondshapes.php

A three year project, running alongside TRAMS, aims to focus on improved productivity and reliability of semiconductor and electronic design, with IBM research to collaborate with seven other members in the DIAMOND ( Development of an Innovative, Accurate, Monolithic New Design?) consortium to create significant savings on chips and cut design time

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Members of the consortium are IBM Research; Ericsson, Sweden; Tallinna Tehnikaulikoo, and Testonica Lab, Estonia; Linkopings Universitet, Sweden; Universitat Bremen, Germany; Technische Universitat Graz, Austria; TransEDA Systems, Hungary.

Jaan Raik, (right) senior researcher at Tallina Techikaulikool and coordinator of the Diamond consortium said that designing semiconductors is very expensive and design costs threaten to slow down the industry's growth.

"The increasing gap between the complexity of new systems and the productivity of system design methods can only be mitigated by developing new and more competent design methods and tools," he said.

"Correctness, already one of the major showstoppers for design, is becoming ever harder to attain," explained (left) Cindy Eisner  senior technical staff member at IBM Research, Haifa and partner in the DIAMOND consortium. "Better debugging techniques must be a major focus in R&D  if we want to keep increasing the scale of electronics design."

Today, approximately 70% of design efforts are dedicated to verification and debugging. Two thirds of this is dedicated to discovering and localising the source of the fault and then correcting it. Another threat is the rapidly growing rate of soft errors, transient errors caused, for example, by cosmic radiation.  

Soft errors cannot be corrected after the fact, but can be dealt with by dedicated detection logic,  measuring robustness of that logic can be dealt with by techniques used for detecting other types of errors. The goal of the DIAMOND consortium is to address these challenges halving fault localisation and correction efforts, to reduce design time by 23%.

Fault localisation and correction for each chip is expected to cost $34.5m per chip by 2010. With DIAMOND aiming to reduce this time by 50%, it has the potential to cut design costs by an estimated $17.25m per chip. Reducing the time spent finding and fixing bugs will also result in significantly shorter design cycle and lower costs as well as shorter time to market.

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