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Dual chip threat: variability and power

Tuesday 2nd August 2011
Professor Asen Asenov shows MOSFET subject to random discrete dopants, line edge roughness and metal gate granularity. The striking image was obtained from the GSS statistical ‘atomistic’ simulator GARAND, the “Gold Standard” in the simulation of statistical CMOS variability. Courtesy: http://www.goldstandardsimulations.com/corporate/founders/

“CMOS Variability Characterisation by Simulations and Measurements” is the August cover story of the flagship IEEE journal Transactions on Electron Devices, warning of statistical variability in CMOS. At The New York Times, John Markoff notes that "Dark Silicon" also threatens faster, cheaper next-generation electronics.

Statistical variability is one of the most acute problems facing conventional (bulk) CMOS technologies. The statistical variability crisis looming at 32nm was prevented by introducing high-k metal gate technology by Intel, which reduced equivalent oxide thickness (EOT) and hence random dopant induced variability. But high-k alone was a short-lived solution to the problem of statistical variability. A new crisis is looms at the 22nm technology generation forciing Intel to introduce FinFETs with reduced statistical variability in order to be able to continue the scaling of SRAM at 22nm.

The cover page of the August special issue on variability of the IEEE Transactions on Electron Devices features the potential and carrier concentration distribution in a 25 nm high-k/metal gate technology 

Four papers featuring results obtained from simulations using GARAND are amongst the 15 variability related papers in the special issue. The GARAND papers cover:

  • The impact of the metal gate granularity on the statistical variability in four generations of scaled bulk MOSFETs;
  •  Statistical enhancement of the simulation of random discrete dopant and line edge roughness induced variability;
  •  Current collapse in bulk MOSFETs due to interaction of the random dopants in the extensions and in the halo pockets and;
  • Variability in nanowire transistors, which are entertained as candidates for sub 10nm CMOS.


Professor Asenov, CEO of GSS and world authority on statistical CMOS variability notes: “Increasing statistical variability and reliability is a formidable threat to future scaling, but is also a great opportunity for the semiconductor companies. Understanding and controlling variability at devices and circuit level can differentiate a semiconductor company from its competitors and provide a clear competitive advantage. GSS is your best bet when dealing with statistical CMOS variability.”

DARK SILICON

Example of a 'conservation core' Courtesy:http://hothardware.com/News/Researchers-Explore-Alternatives-To-Dark-Silicon/

"For decades," writes  Markoff, "the power of computers has grown at a staggering rate as designers have managed to squeeze ever more and ever tinier transistors onto a silicon chip — doubling the number every two years, on average, and leading the way to increasingly powerful and inexpensive personal computers, laptops and smartphones.

A paper at the International Symposium on Computer Architecture on Dark Silicon  summed up the problem: the most advanced microprocessor chips have so many transistors it is impractical to supply power to all of them at the same time. So some of the transistors are left unpowered — or dark, in industry parlance — while the others are working. The phenomenon is known as dark silicon.

As early as next year, advanced chips need 21% of their transistors to go dark at any one time, according to the paper's researchers who wrote the paper. And in just three more chip generations — a little more than a half-decade — the constraints will become even more severe. There will be vastly more transistors on each chip, as many as half of them will have to be turned off to avoid overheating.

Moore’s Law that transistors on an integrated circuit chip would double roughly every two years, bringing exponential improvements in consumer electronics means any lag to that and innovation may slow considerable. No new PCs, new smartphones, new LCD TVs, new MP3 players or whatever might become the new gadget that creates an overnight multibillion-dollar industry and tens of thousands of jobs.

In their paper, Dr. Doug Burger  (Microsoft Research and fellow researchers simulated the electricity used by more than 150 popular microprocessors and estimated that by 2024 computing speed would increase only 7.9 times, on average.

By contrast, if there were no limits on the capabilities of the transistors, the maximum potential speedup would be nearly 47 times, the researchers said.

A variety of new design ideas would help ease the limits identified and Intel recently developed a way to vary the power consumed by different parts of a processor, allowing for both slower, lower-power transistors as well as faster-switching ones that consume more power.

Processor chips contain two or more cores making it possible to use multiple programs simultaneously. Intel computers will have different kinds of cores optimized for different kinds of problems, only some of which require high power. 

Now for next-generation brains to innovate the solutions.

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