The ’Statistical Design and Verification of Analogue Systems’ (StatDes) project aims to improve  electronic and electrical systems design, specifically looking at the problem of statistical variability in transistors, an expertise area of Gold Standard Simulations while Calvatec's Andy Cringean has enormous expertise focused on dramatic reduction of design and manufacture costs in complex, mixed-signal, System-on-Chip integrated circuits.

The project will transfer knowledge gained in the NanoCMOS project, an initiative funded by Engineering and Physical Sciences Research Council to tackle variability in digital systems, to electronics-design companies in Scotland.

Increased silicon chip performance is due to transistor shrink but simultaneously tiny variations and structural flaws impact performance.

Engineers at Wolfson Microelectronics and IBM will work with the StatDes academic team to develop tools to analyse analogue systems, transmitter/receiver circuits — using advanced simulation technology and Gold Standard Simulations (GSS), software tools and approach.

Prof Asen Asenov, James Watt chair in electrical engineering, College of Science and Engineering at Glasgow University, says: "The real world remains a stubbornly analogue place. Analogue systems are extremely sensitive to variability and we must tackle this issue for the electronic systems of the future."

The first phase of the project will bring the benefit from the knowledge gained by the Glasgow and Edinburgh university researchers to Wolfson Microelectronics and Gold Standard Simulations. Later phases will see information disseminated to manufacturers, Freescale, Elonics, Inside, Ateeda and Dukosi.

It is hoped  the project will establishing an industry focused research centre to continue future partnership work.