Laser separation, electrografting, nanospray, and multiple process integration
Three of of eight finalists in the SEMI Best of West awards were from Europe and were for new packaging technologies — three in 3-D IC applications and one from the US was in process integration. They were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact. Three of these are sourced from Europe.
Jenoptik Automatisierungstechnik GmbH from Germany introduced a wafer dicing system that uses thermal laser separation (TLS). The Jenoptik-Votan G Semi was developed as an alternative to the established mechanical dicing saws and any other laser dicing technologies to deliver a more precise cutting edge. It is claimed well suited for applications with special demands on edge quality, such as optical devices or power devices with vertical current flow. The TLS process is clean and free of vibrations or mechanical shock waves, and can be used for MEMS products. The technology also minimises the amount of water and other consumables compared with mechanical dicing. The process works for most silicon wafer-based PV cells, as well as SiC and GaAs wafers.
TLS wafer dicing increases throughput and lower cost of ownership. The yield becomes higher by using the zero width of the separation line and reducing the dicing street width. The development of this product is supported by a project of the European Union (“SEA NET”, IST-027982).
Several Best of West Award entries addressed the emerging needs for through-silicon via (TSV) manufacturing, including the eG ViaCoat from Alchimer (Massy, France) for the electrografting of copper seed layers used for the metallization of TSVs.
Metallization of TSVs is an enabling process for 3-D stacking, and relies on the formation of a thin copper seed layer over the surface of the via. At high aspect ratios, this is a real challenge for dry vacuum processes and can be even more acute for Bosch-etched TSVs, where a PVD line-of-sight process needs to deposit a continuous and conformal film on scalloped sidewalls.
According to Alchimer, a conventional PVD tool without expensive resputtering capability cannot reliably coat 
scalloped TSVs with aspect ratios above 3:1. ALD and CVD techniques are expensive and slow, and currently do not exist for copper seed deposition. Alchimer uses electrografting, a wet electrochemical process based on specific organic precursors to enable the initiation and growth of thin films on conducting and semiconducting surfaces. The process produces conformal, thin, uniform and adherent layers, even on resistive barriers.
The eG ViaCoat enables low-resistivity copper seed layers in the 50-500nm range to be deposited on various barrier materials with very high adhesion. Continuous coverage of high-aspect-ratio (>10:1) TSVs claims be achieved, enabling subsequent void-free copper via filling.
A unique capability to deposit a continuous copper seed layer on discontinuous layers, widens the process window for PVD-deposited barrier and adhesion layers, even on “scalloped” TSV etch profiles. Conformal sidewall and bottom coverage have been demonstrated, even on highly scalloped TSV etch profiles and at aggressive TSV aspect ratios. While the coating of vertical features is common practice in MEMS technology, it has been adopted in emerging advanced packaging and interconnect arenas. Above: Courtesy: http://www.alchimer.com/
Below: Courtesy http://www.evgroup.com/
The EVG150 NanoSpray System from EV Group (St. Florian, Austria) is a photoresist application system that will enable users to carry out further lithography steps at the bottom of vias to create through-wafer interconnects and allow a new bandwidth of applications in many semiconductor processing markets. The system enables fully automated, high-topography spray coating for very small and deep patterns from 300 µm deep and 100 µm diameter.
This coating technology was first realized by EVG on their EVG100 series coating equipment by development and integration of new spray technology and techniques. First systems have been installed at major customers, and are being used to manufacture CMOS imaging sensor (CIS) packages based on TSV technology.
At this early stage of TSV commercialization, bridging the gap between R&D and production manufacturing processes will be a major challenge for many applications. Addressing this need, Versalis fxP from Aviza Technology (Scotts Valley, Calif.) has developed a single-wafer cluster system that integrates multiple processes (including etch, PVD and CVD) on a single platform.
Targeted for advanced R&D activities, the single-platform solution allows customers to develop their TSV processes
in an efficient manner in the lab with the ability to seamlessly migrate to high-volume production. According to Aviza, this “one-stop shop” solution enables customers to save money by investing in less capital expenditures for R&D, minimising installation costs and making efficient use of fab area.
The Versalis fxP is based on Aviza’s single-wafer platform that provides individual modules such as deep silicon etch, PVD and CVD that are currently in use in high-volume manufacturing for various applications including wafer-level packaging, MEMS and power semiconductors.
The Versalis fxP system (Right Courtesy: http://www.aviza.com/www.aviza.com/) allows R&D users to link processes in a way that would not be possible on traditionally configured single-process systems. On the Versalis fxP, users can link separate processes without breaking vacuum to discover potential performance benefits, and then apply those findings to optimally configure production tools.
Source: http://www.semiconductor.net/article/CA6577631.html?industryid=47304&nid=3572