The presentation at IEDM will be given David Reid (right) who is a PhD student in Professor Asenov's group. Developed through the EPSRC funded UK £5.3m e-Science project NanoCMOS  the e-Science pilot project led by Professor Asen Asenov and his 30 strong researcher team at the University of Glasgow has developed an advanced Grid-based e-Infrastructure allowing, for the first time, 3D simulation of hundreds of thousands of microscopically different transistors.

This gives unprecedented analysis and exploration of statistical CMOS statistical variability associated with the discreteness of charge and granularity of matter in today’s mass production computer and consumer electronics silicon chips featuring 30nm channel length transistors.

Numerical simulations have long played a key role in understanding statistical CMOS variability and in predicting its impact on future technology generations with modern computer and consumer electronics chips now containing billions of transistors. The simulation results have helped chip designers develop strategies that allow the design of reliable systems on a chip (SoC) whilst using the less reliable and more variable next generation nano CMOS transistors.

But due to the enormous complexity and computer requirements of such 3D simulations, previously simulation approaches were restricted to small statistical samples of approximately 100 transistors, insufficient to predict the tails of statistical distributions which are of tremendous importance for the overall reliability and yield of modern SoC products, which need to be designed to 6-7 sigma specifications.

Such simulations were reported at by Professor Asenov at “Challenges for silicon technology scaling in the Nanoscale Era” at ESSDERC/ESSICRC in March this year, in the paper “Understanding LER-induced Statistical Variability: A 35,000 Sample 3D Simulation Study” and was carried out on widely distributed high performance computing clusters with thousands of processors, consuming more than 20 years of CPU time in a few weeks period, to reveal unknown details of the statistical behaviour of nano CMOS transistors subjected to line edge roughness [1].

Below: 3D simulation of random dopant effects in a 45 nm technology pMOSFET. All individual dopants in the transistor are visible. Blue dots – acceptors, read dots – donors.

An article highlighting new features of the random dopant induced statistical variability “Analysis of the Random Dopant Induced Threshold Voltage Distribution Tails: A 105 Samples Size 3D Simulation Study” published in October IEEE Transaction on Electron Devices Development, [2] and Professor Asenov’s oral presentation at IEDM will further reveal important details of the interaction between random discrete dopants and line edge roughness in contemporary CMOS transistors [3].

“ Nano CMOS Grid technology has helped not only to understand for the first time intimate details of the CMOS statistical variability, but also to develop statistically enhanced algorithms that will allow accurate prediction of statistical variability with greatly reduced computational efforts. This will be to the great benefit not only of the major semiconductor manufacturers but also to the vibrant UK design industry that is facing the increasing challenges of the modern nano CMOS technology and design” said Professor Asenov.

“The NanoCMOS project has pushed the envelope for large scale simulations and data management in the engineering domain. I am delighted that we have advanced the state of the art in understanding and modelling of statistical CMOS variability and helping to address the highest priorities facing the semiconductor industry” said Professor Richard Sinnott, the NanoCMOS e-Science director.

Gold Standard Simulations launch
The Glasgow simulation tools and the grid based simulation technology are
in the heart of a new €26M European project MODERN (MOdeling and DEsign of Reliable, process variationaware Nanoelectronic devices, circuits and systems) funded by the European Nanoelectronics Initiative Advisory Council (ENIAC) Joint Technology Undertaking (JTI) initiative.

The project, which will run until early 2012, has 28 partners from nine European countries. The first ENIAC JTI call, that lead to the funding of MODERN, was inspired by the research of Professor Asenov and the NanoCMOS project.

Despite the fact that the UK decided not to participate in the first ENIAC call, a special funding package of £1.43m was created jointly by EPSRC and Scottish Enterprise for Professor Assenov’s group ensuring their leading role in the nano CMOS variability research in Europe and worldwide.

The Scottish Enterprise funding will facilitate the creation of a spin-out company, Gold Standard Simulations (GSS) to commercialise the world leading variability simulation tools developed at Glasgow.

Professor Asenov's Device Modelling Group at Glasgow has developed unique variability simulation tools and strong partnership with the leading semiconductor manufacturers, and is now involved in just about every major European project looking at this problem.

‘I knew this would be a big problem in the future,’ he says. ‘My group was the first group in the world to look systematically at this issue and my first single-authored paper on this subject, [based on research that I conducted in my spare time without any funding,] is the most referenced paper on statistical variability ever written.’

Statistical variations between transistors mainly occur due to the
random number and position of discrete dopants – chemicals introduced in the silicon of which the microchips are made to form the structure of the transistors. Variations in the numbers and positions of individual atoms within the transistor can result in disruption and variations to the current flow.

It becomes impossible to predict the characteristics of the individual nano-transistors in the chip and this makes the design of the integrated circuits increasingly difficult, resulting in poor yield and chip failures.

Apart from random dopants, imperfections in the transistor geometry definition (line edge roughness) and the nanoscaled granularity of
the materials from which part of the transistors are made are becoming increasingly important contributors to the statistical variability.

Predicting the magnitude of statistical variability in the future and helping the designers to deliver reliable chips made of unreliable transistors is where Professor Asenov and his team excel and of particular importance to the vibrant UK chip design industry with world leading chipless and fabless design housed like ARM, CSR and Wolfson Microelectronics

References:
[1] Dave Reid, Campbell Millar, Gareth Roy, Scott Roy and Asen Asenov, Understanding LER-induced Statistical Variability: A 35,000 Sample 3D Simulation Study, Proc. ESSDERC’09 pp. 423-426 (2009)
[2] Dave Reid, Campbell Millar, Gareth Roy, Scott Roy and Asen Asenov, Analysis of the Random Dopant Induced Threshold Voltage Distribution Tails: A 105 Samples Size 3D Simulation Study, IEEE Trans. Electron Dev. Vol. 56 (Oct 2009)
[3] Dave Reid, Campbell Millar, Gareth Roy, Scott Roy and Asen Asenov, "Statistical enhancement of combined simulations of RDD and LER variability: What can simulation of a 105 sample teach us?" IEDM 2009.

For further information:

NanoCMOS, funded by the UK Engineering and Physical Sciences Research Council (EPSRC) in collaboration with leading design houses, chip manufactures and ECAD vendors is funding a £5.3M to apply Grid and eScience technologies and know-how to tackle some of the fundamental challenges of nano-CMOS design.

The university partners in this project include the Device Modelling and the Microsystems Technology groups (University of Glasgow), the Advanced Processor Technologies group (University of Manchester), the Electronic Systems Design Group (University of Southampton), the Intelligent Systems group (University of York), the Mixed-Mode Design Group (University of Edinburgh).

The e-Science and Grid technology is provided by the National e-Science Centre (at the universities of Glasgow/Edinburgh) and the e-Science North West (Manchester University).

Two of the largest UK chip design companies ARM and Wolfson Electronics;  world leader in design software Synopsys, and leading semiconductor chip manufacturers, Freescale, National Semiconductors and Fujtsu are industrial partners.