With this program an initial offering of SOI intellectual property has been provided by IBM (embedded dram) ARM (memory compilers, I/O libraries, power management) and Cadence Design Systems. More IP has been added by Boeing and Synopsys, with an invitation extended to other developers to add to this growing SOI IP ecosystem.

SOI process technology can improve chip performance up to 30% and 40% power reduction compared to bulk silicon technology. The Ready for SOI program is now to making necessary design building blocks available to a broader population of chip designers to harness SOI  benefits for new applications, including mobile and consumer products.



Key enabler for this effort is the new SOI Portal hosted on the popular ChipEstimate.com The SOI Portal provides chip designers access to available design building blocks and to the companies supporting chip development on SOI processes.

“ChipEstimate.com has become a critical resource to over 26,000 registered SoC designers by providing central access to over 200 of the world’s largest IP suppliers and foundries,” said (right) Adam Traidman, CEO and President  “Our new SOI micro-site will serve as an invaluable resource to designers wishing to explore the benefits of SOI technology for their chip design projects.” 



To help IP and chip designers transition to SOI, the Ready for SOI program is sponsoring SOI Jump Start Training hosted by Cadence on April 28, 2010 at the Cadence Engineering Center Auditorium, in San Jose, CA.
 
“We are removing a barrier to industry adoption by giving all chip designers access to the benefits of SOI, not just those working for integrated device manufacturers and high-end ASIC developers,” says Horacio Mendez, (left) executive director of SOI Industry Consortium.

“Through the enablement provided by ARM’s SOI libraries and EDA tool suppliers, a vast range of synthesizable IP is now easily portable to SOI technology and physical IP can be readily ported or designed using industry standard tools.”

Another obstacle had been access to SOI process technology, but according to Mendez, this has been addressed with foundries such as IBM, Globalfoundries and Chartered offering services.



“IBM was the first company to ship SOI products and we are now in our seventh generation of this leading technology,” said (right) Michael Cadigan,GM, IBM Microelectronics division. “Through this collaboration with ARM, Cadence and other suppliers, we are providing an open design system and a proven supply chain to bring the significant performance and power-saving advantages of SOI technology to clients developing mobile and other system-on-chip applications.”

The SOI Industry Consortium invites all chip designers to evaluate the advantages of SOI for their next design by visiting the SOI Portal. Digital, analog and mixed-signal IP suppliers are invited to participate in listing their offerings on the SOI Portal. Designers worldwide invited to register and attend the SOI Jump Start training on April 28, 2010 with the option of attending a live event in Silicon Valley hosted by Cadence, or online in a simulcast or recorded webinar.