Duallogic, a top-ranked project, is the ‘flagship’ of CMOS R&D in FP7. The European consortium project led by Dr Athanasios Dimoulas, National Center for Scientific Research DEMOKRITOS, IMEC, IBM-Zurich, CEA-LETI, STMicroelectronics, NXP Semiconductors, AIXTRON, University of Glasgow and Katholieke Universiteit Leuven have an EC grant of €5.8m and 36 months to tackle the challenge.

At the end of 2007, what Gordon Moore described as the “biggest change in transistor technology in 40 years”: the 45nm CMOS generation, came into production, with a metal/high-k dielectric combination in the gate, instead of the polySi/SiO2 which, for many years, was considered to be irreplaceable.

If the gate dielectric ‘heart’ of the transistor could be changed, eventually any other part can be changed too. The active channel may be next up for replacement to break performance barriers beyond the 22 nm node.

Charge carriers in Germanium have higher mobility, but after five years of intensive research, it turns out that Ge only outperforms Si for pMOS and a CMOS technology entirely of Ge does not seem currently viable. But other semiconductors such as III-V compounds (Gallium Arsenide, Indium Gallium Arsenide) are effective for nMOS, but have seemed to be unsuitable for pMOS. Contrary to recent belief, Ge and III-V compound semiconductors are not competitors; but  materials which could complement each other on the same chip.

Recognising this, Duallogic researchers will attempt co-integration of Ge pMOS and III-V nMOS side-by-side on a complex engineered substrate on silicon ,to demonstrate for the first time a dual-channel CMOS technology.
The main aim of the project will be to demonstrate that high mobility dual-channel, front-end-of-line CMOS technology is scalable and manufacturable, by employing a Si-compatible process in a 65nm/200mm pilot line.

In the first stage CEA-LETI and STM will work on the development of the 200mm local GeO1 by Ge condensation. while second step Aixstron works on development of the MOCVD equipment and processes for selective epitaxy of III-V compounds on Ge with IMEC sorking on dual channel engineered substrates. The third step involves IMEC and IBM working on cointegration in the 65nm/200mm pilot line. Underpinning this is University of Leuven working on the development of the gate stack while NXP Semiconductor and University of Glasgow undertakes device modelling and circuit design respectively.

The consortium expects Duallogic will determine by the end of 2009 whether the high mobility dual-channel approach is a viable option for CMOS beyond 22 nm. This could stimulate further development into a wider
sub-22nm technology platform by integrating dual channel FEOL with back-end and device architecture modules within a future and larger R&D initiative in Europe.

Besides high mobility, the channel materials under investigation in this project have several other interesting properties which make them attractive beyond the context of device scaling for logic as, for example, in applications where lower supply voltages are needed to combine low power with high performance.

Because of this, DUALLOGIC could create a generic material and technology platform which could allow a significant diversification on the chip with added functionality. And it could be the catalyst for the convergence of 2020 nanoelectronic technologies as foreseen in the ambitious research agenda of Europe’s ENIAC technology platform.

Web:http://www.ims.demokritos.gr/DUALLOGIC
Dr. Athanasios Dimoulas
e-mail: dimoulas@ims.demokritos.gr

For the University of Glasgow, Duallogic is only the first of  three projects which could revolutionise the electronics industry. The European Commission has provided £750,000 funding for three projects, including  NANOSIL and REALITY, which will support research aimed at creating a new generation of faster and bigger electronic chips that power all consumer electronics products.

Lead investigator of the Glasgow side of the projects, Professor Asen Asenov
said: “This funding is really important for the UK electronics industry which suffers from relatively low level of investment in semiconductor device and technology research. The European Commission recognises that University of Glasgow researchers are world-leaders in the area of chip development, known as nano CMOS device modelling and novel device technology and design.

The projects will be run in collaboration with leading European manufacturers and research institutes. The funding was provided through the first call of proposals in the European Commission’s Seventh Framework Program (FP7) for collaborative European research in the area of Information and Communication Technologies. NANOSIL and REALITY will be launched later this year.

Professor Asen Asenov
e-mail: A.Asenov@elec.gla.ac.uk